- Research Interests
- Parallel and Distributed Simulation, Digital Logic Verification, Dynamic Load Balancing, General Purpose-computing Graphics Processing Units (GPGPUs), Multi-Core processors, Machine Learning, Reinforcement Learning
- Profile
- I am a Ph.D. student in School of Computer Science of McGill university. My current PhD advisor is professor Carl Tropper.
I obtained an MSc degree from the Sharif University of Technology , Department of Computer Engineering, and two BScs degrees from the Computer Engineering and
Industrial Engineering departments of AmirKabir University of Technology. My current research interest is in the area of parallel digital logic simulation. I design optimistic parallel simulators to verify the correctness of Verilog designs. Dynamic load balancing during the course of the simulation is also at the core of my research. I am also applying learning techniques (e.g. Reinforcement Learning ) to improve the performance of the parallel gate level simulation. I also plan to study the performance of parallel algorithms for digital logic verification on multi-core and General Purpose-computing Graphics Processing Unit (GPGPU) platforms.
- Current Research Project
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One of the important steps in the design process of current Integrated Circuits(IC) is the verification of their correctness by simulation. Unfortunately, the performance of a sequential simulation degrades when the size and complexity of the system being simulated increases. As current digital circuits have millions of gates, the memory demand and the need for decreased simulation time are major challenges for the verification process. On the other hand, parallel discrete event simulation has emerged as a viable alternative to provide a fast, cost effective approach for the simulation of large designs. It is necessary to synchronize the processes which comprise a parallel simulation. In my thesis, I utilized an optimistic synchronization approach called Time Warp, for parallel digital logic simulation.
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Verilog and VHDL are the two major HDLs used for the design of integrated circuits. I developed a parallel time warp Verilog simulator and examined the performance of the simulator on large designs (Sun’s open source LEON, OPEN SPARC Processors, a large FFT design) on a simulation environment with 32 dual-core Intel processors. We established that the simulator’s performance for these large designs is scalable. It is important to note that to date only small benchmark circuits and synthetic circuits were available for parallel optimistic circuit simulation; our use of these designs was much more realistic.
It is well known that balancing the load throughout the course of a parallel simulation is of fundamental importance. Circuit simulation is no exception to this rule; large load imbalances were observed throughout the course of our experiments. Consequently, I developed two dynamic load balancing algorithms to balance the computation and communication loads during the simulation. In both of the algorithms, all of the nodes in the simulation forward their computation and communication information to a central node. The central node creates a set of overloaded and under-loaded processors and put the nodes in these two sets. A graph bipartite matching algorithm is utilized to match the processors of these two sets. Finally, each processor in the overloaded set utilized its local data and forwards some load to its match. Our simulation results indicate up to 20% improvement in simulation time as a direct consequence of these algorithms.
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Our experiments indicated that for various circuits and simulation environments (e.g. number of nodes on the parallel computer), we needed different values for the tuning parameters of the dynamic load balancing algorithm in order to get the best result. As the first attempt to compute these parameters, we utilized reinforcement learning. Reinforcement Learning (RL) is an area of Artificial Intelligence which is concerned with the interaction of an agent with its environment. The agent takes actions which cause changes in the environment and the environment, in its turn, sends numerical responses to the agent indicating the effectiveness of its actions. The actions in our case are the choice of different values for the control parameters. In contrast to adaptive methods, these techniques do not depend upon an analytical model of the system being simulated. Instead, they learn directly from experience with the system for which they are employed. Different techniques for solving the reinforcement learning problem and tuning the parameters of the dynamic load balancing algorithm are described in the thesis. Among these techniques, the N-Armed bandit and multi-state Q-learning exhibited the best performance.. We reduced the simulation time up to 34% for LEON processor using the N-Armed bandit method. Applying a multi-state Q-learning approach the simulation time was reduced up to 42% for OpenSparc processor.
