As usual, the "s" suffix after each mnemonic stands for "size", which can be either a byte, word or long word. The logical operations are bitwise in the obvious sense, that is, bit 0 of the source is "anded" with bit 0 of the destination, and so on. The only bits affected by such an operation are the ones concerned by it; if the size specified is a byte, then only the least significant byte of the destination will be affected, and if the size is a word, then only the least significant word of the destination will be affected. For "and" and "or" (which is the inclusive or), at least one of the operand must be a data register; for "eor" (the exclusive or), the source operand must be a data register. This is the only place where these instructions do not agree.

The source operand can be anything but an address register. The destination operand can be anything except an address register, a constant or a memory location specified through a program counter indirect addressing mode.

All operations above set the condition code bits as follows:

X is not affected;
N is set if the result is negative, checking the most significant bit of the result;
Z is set if the result is zero; cleared otherwise;
V & C are always cleared.

The warning issued in the "data movement" section about the size of the operands affecting the condition codes also applies here.

example 6.1: andb sp@ +, d0

The instruction above pops a byte off the stack, and "ands" it to the lest significant byte of register d0. Suppose the byte popped was valued "0"; then the least significant byte of d0 should be set to "0" by it, and the "Z" flag will be set, even if the 32-bit quantity held by d0 as a whole is not equal to "0".

We can also combine the logical operators with a constant, with the instructions

#constant, destination

All three operand sizes are allowed; they specify to the processor what proportion of the destination should be affected, in the usual way. The constant must be specified using the syntax shown in the "addressing modes" section. The destination operand can be anything except an address register, a constant or a memory location specified through a program counter indirect addressing mode. The condition codes behave in the same way as in the ordinary logical instructions.

Note that we dont have to use this instruction for such a purpose; we can use the more general ones defined previously, and the assembler will replace them when it needs to. For example, the NeXT assembler will automatically translate an "andl #2, d0" into "andil #2, d0". Strangely enough, it will even translate "eorl #2, d0" into "eoril #2, d0", even though the former is not legal according to the Motorola specifications.

Finally, we can combine a constant and the condition code register in a logical operation, with the instructions.

#constant

As you can see, the only size allowed is a byte, and the CCR has to be the destination. The constant can be anything that fits in 32 bits. The condition code bits are set according to the operation and the constant, of course.

Unary Operator

The only one is the negation; the syntax of the instruction is

s operand

This simply inverts all the bits included in the operand size. The size can be a byte, a word, or a long world. The least significant one is the only one affected, be it byte or word. The operand can be anything except an address register, a constant or a memory location accessed through a program counter indirect addressing mode. The condition code bits have the same behavior as for the other general logical operations.

The "clear" instruction

The description of this instruction could as well have been given in the "integer arithmetic" section. Some of the instructions are so general that it becomes hard to put them in a specific category.

The syntax of it is

operand

It basically has the same effect as a "move #0, operand". The size of the operand can be a byte, a word or a long word. The operands allowed are the same as in the "not" instruction. The condition code bits are set as follows:

X is not affected;
Z is always set;
N, V & C are always cleared.

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